This application claims benefit of priority under 35USC xc2xa7 119 to Japanese Patent Application No. 1999-342573 filed on Dec. 1, 1999 in Japan, the entire contents of which are incorporated by reference herein.
The present invention relates to a signal voltage-level shifter and a semiconductor memory using the shifter.
Several electrically-erasable non-volatile semiconductor memories (EEPROM) have been known. Each memory cell of EEPROMs is constituted by a MOS transistor having stacked floating and control gates. A memory cell array can be formed by connecting a plurality of memory cells in NOR- or NAND-type. Both types of memory cell array require several internal boosted high voltages and negative voltages according to operation mode, such as, data programming and erasing.
A NOR-type EEPROM operates as follows: Voltages at 5V and 9V are applied to the drain and the control gate, respectively, of a selected memory cell while the source is grounded, for data programming. This voltage application allows hot electrons to be injected into the floating gate to shift a threshold level of the selected memory cell toward a positive level, which is a programmed state, such as, a xe2x80x9c0xe2x80x9d-state.
Data programming includes a data verification operation to verify that data has been programmed. The verification operation applies a voltage, such as, 6.5V, to the control gate, that is higher than that for a regular data reading operation to judge whether the programmed data is xe2x80x9c0xe2x80x9d or not. Data programming is performed again if programming is insufficient.
Concerning data erasing, all data are usually erased for each unit of block. Voltages at xe2x88x927V and 5V are applied to the control gate and the common source, respectively, while the drain is floating in each memory cell in a selected block.
This voltage application allows electrons in the floating gate to be discharged to the source with a tunnel current to shift a threshold level of the selected memory cell toward a negative level, which is an erased state, such as xe2x80x9c1xe2x80x9d-state. The same can be done by applying, for example, 10V to the source and well regions, electrons being discharged from the entire channel region with a tunnel current.
Data erasing also includes a data verification operation to verify that data has been erased. The verification operation applied a voltage, such as, 4V, to the control gate, that is lower than that for a regular data reading operation to judge whether the memory cell in the erased block is xe2x80x9c1xe2x80x9d or not. Data erasing is performed again if insufficient.
Over-erasing occurs to memory cells that are easily erased among blocks to be erased. An over-erased memory cell, having a negative threshold level at which a current flows even at 0V to the control gate, obstructs a regular reading operation due to a leakage from a non-selected cell when 0V and a voltage for reading are applied to the control gates of the non-selected cell and a selected cell in a xe2x80x9c0xe2x80x9d-state, respectively, thus resulting in erroneous reading of a xe2x80x9c1xe2x80x9d-state from the xe2x80x9c0xe2x80x9d-state selected cell.
A weak programming is performed to ease an over-erased state or an over-erased memory cell. One technique is to apply 0V and 5V to the control gate and the corresponding bit line, respectively, to set memory cells connected to the bit line to meet a weak programming requirement. This technique utilizes potential rising at the floating gate due to capacitance-coupling from the drain, which is called a self-convergence technique due to that fact that electrons injected into the floating gate decrease its potential so that the programming requirement is not met.
Another technique to ease an over-erased state of an over-erased memory cell is to apply 3V and 5V to the control gate and the drain, respectively, to set selected memory cells to meet a weak programming requirement. This voltage application allows hot electrons to be injected into the floating of an over-erased memory cell to ease the over-erased state. This technique requires a voltage of, for example, xe2x88x921.5V, to the control gate of non-selected cells for non-selected over-erased cells not to be turned on.
FIG. 1 represents Vgs-to-Ids characteristics for several states of EEPROM as described above.
A normally programmed state xe2x80x9c0xe2x80x9d and a normally erased state xe2x80x9c1xe2x80x9d are represented by OFF and ON, respectively, for a voltage Vread for reading applied to the control gate. An over-erased state is a state in which electrons have been discharged until the threshold level becomes negative. Self convergence state (1) and weak program state (2) represent a weak programming and an active programming, respectively, under the self-convergence technique.
As discussed, EEPROMs use variety of voltages according to operation modes. EEPROMs have a chip-in-voltage booster for generating several high voltages and also a chip-in-voltage-level shifter in an address decoder for shifting VCC-VSS amplitude signal voltage to control voltages of several levels.
For example, as shown in a well-known circuit in FIG. 2, a first voltage-level shifter 2 and a second voltage-level shifter 3 are connected to the output of a row decoder 1 for selectively activating word lines.
The row decoder 1 performs an identification operation to addresses A0, A1, . . . , to output complimentary decode output signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d having an amplitude of VCC-VSS.
The signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are supplied to the first voltage-level shifter 2 and converted into signals xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d, respectively, having a potential VSW higher than the high level of the corresponding signal xe2x80x9caxe2x80x9d or xe2x80x9cbxe2x80x9d. The potential VSW is a high potential for programming and supplied by a voltage booster (not shown), which will become a potential Vread in reading.
The signals xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d are supplied to the second voltage-level shifter 3 and converted into signals xe2x80x9cOUTAxe2x80x9d and xe2x80x9cOUTBxe2x80x9d, respectively, having a potential VBB lower than the low level of the corresponding signal xe2x80x9cAxe2x80x9d or xe2x80x9cBxe2x80x9d. At least either the signal xe2x80x9cOUTAxe2x80x9d or xe2x80x9cOUTBxe2x80x9d is supplied to a word line driver (not shown).
The first voltage-level shifter 2 consists of NMOS transistors QN1 and QN2 provided at the VSS-side, that receive the signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d, respectively, and PMOS transistors QP1 and QP2 provided at the VSW-side. The transistors QP1 and QP2 constitute a flip-flop in which the gate and drains are cross-connected for positive feed-back to shift the high-level potential of the signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d from VCC to VSW.
The second voltage-level shifter 3 consists of PMOS transistors QP3 and QP4 provided at the high-level VSW-side, that receive the signals xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d, respectively, and NMOS transistors QN3 and QN4 provided at the low-level VBB-side. The transistors QN3 and QN42 constitute a flip-flop in which the gate and drains are cross-connected to shift the low-level potential xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d from VSS to VBB.
The voltage-level shifters 2 and 3 are, however, are disadvantageous for an unstable switching operation in voltage-level shifting.
This disadvantage is discussed in detail with respect to the second voltage-level shifter 3 for low-level side shifting.
FIG. 3 represents voltage-to-current characteristics of the PMOS transistor QP3 and the NMOS transistor QN3. The curve C1 represents a static characteristic when a gate voltage Vg supplied to the NMOS transistors QN3 is VSW. The curve C2 is a load characteristic curve given by the PMOS transistor QP3 the conductance of which is controlled by the input signal xe2x80x9cAxe2x80x9d.
The signs I1 and I2 represent a current at a voltage 0V (xe2x80x9cAxe2x80x9d=VSS) to the PMOS transistor QP3 on the load characteristic curve C2 and a current at a voltage 0V to the NMOS transistor QN3 on the static characteristic C1, respectively.
A normal voltage-level shifting for the second voltage-level shifter 3 must meet the requirement I1 greater than I2. If I1xe2x89xa6I2, the transistors QP3 and QP4 are tuned off and on, respectively, thus the transistors QN3 and QN4 are tuned on and off, respectively, at xe2x80x9cAxe2x80x9d=VSW and xe2x80x9cBxe2x80x9d=VSS.
Inversion of the input signals to the second voltage-level shifter 3 hardly turns off and on the transistors QN3 and QN4, respectively. This is because the low level of the input signal xe2x80x9cAxe2x80x9d to the PMOS transistors QP3 is VSS, and, and indicated in FIG. 3, the transistors QP3 cannot produce a current more than the current I1; and moreover, the NOMS transistors QN3 has been tuned on by means of the negative potential VBB supplied to its source and is hardly turned off.
There are some ways to overcome the disadvantage discussed above, such as, providing PMOS transistors QP3 and QP4 having large current capacity or keeping VSS until the low-level side potential VBB is supplied after the transition of the circuit shown in FIG. 2.
The former way, however, increases a layout area on a chip, and the latter increases time for data programming control, etc.
A purpose of the present invention is to provide a voltage-level shifter having an accurate voltage-level shifting operation with no increase in chip area and time for control.
Another purpose of the present invention is to provide a semiconductor memory housing such a voltage-level shifter.
The present invention provides a voltage-level shifter including: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials: a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal; as first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal; a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal; a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal; a third NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the first NMOS transistor, and a gate connected to the second output terminal; and a fourth NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the second NMOS transistor, and a gate connected to the first output terminal.
Moreover, the present invention provides a voltage-level shifter including: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal; a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal; a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the second output terminal; a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the first output terminal; a third NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the first NMOS transistor, and a gate connected to the first input terminal; and a fourth NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the second NMOS transistor, and a gate connected to the second input terminal.
Furthermore, the voltage-level shifter including: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which is a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal; a first NMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal; a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first PMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal; a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal; a third PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the first PMOS transistor, and a gate connected to the second output terminal; and a fourth PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the second PMOS transistor, and a gate connected to the first output terminal.
Moreover, the present invention provides a voltage-level shifter including: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level with respect to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal; a first NMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal; a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first PMOS transistor having a drain connected to the first output terminal and a gate connected to the second output terminal; a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the first output terminal; a third PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the first PMOS transistor, and a gate connected to the first input terminal; and a fourth PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the second PMOS transistor, and a gate connected to the second input terminal.
Moreover, the present invention provides a semiconductor memory including: a memory cell array having a plurality of electrically-rewritable memory cells; a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines a bit lines of the memory cell array; a first voltage-level shifter that shifts a high level of the decoded output signal for selecting at least one of the word lines to a further high level according to an operation mode to output a first voltage-level shifted output signal; a second voltage-level shifter that shifts a low level of the first voltage-level shifted output signal to a further low level according to the operation mode to output a second voltage-level shifted output signal; and a word line driver that is controlled by the second voltage-level shifted output signal to drive that selected word line, wherein the first voltage-level shifter includes: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which the decoded output signal is supplied, the decoded output signal having a high and a low level according to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the decoded output signal; a first NMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal as the first voltage-level shifted output signal; a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first PMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal; a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal; a third PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the first PMOS transistor, and a gate connected to the second output terminal; and a fourth PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the second PMOS transistor, and a gate connected to the first output terminal.
Furthermore, the present invention provides a semiconductor memory including: a memory cell array having a plurality of electrically-rewritable memory cells; a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines and bit lines of the memory cell array; a first voltage-level shifter that shifts a high level of the decoded output signal for selecting at least one of the word lines to a further high level according to an operation mode to output a first voltage-level shifted output signal; a second voltage-level shifter that shifts a low level of the first voltage-level shifted output signal to a further low level according to the operation mode to output a second voltage-level shifted output signal; and a word line driver that is controlled by the second voltage-level shifted output signal to drive the selected word line, wherein the second voltage-level shifter includes: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which the first voltage-level shifted output signal is supplied, the first voltage-level shifted output signal having a high and a low level according to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first voltage-level shifted output signal; a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal; a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal; a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal; a third NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the first NMOS transistor, and a gate connected to the second output terminal; and a fourth NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the second NMOS transistor, and a gate connected to the first output terminal.
Moreover, the present invention provides a semiconductor memory including: a memory cell array having a plurality of electrically-rewritable memory cells; a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines and bit lines of the memory cell array: a first voltage-level shifter that shifts a low level of the decoded output signal for selecting at least one of the word lines to a further low level according to an operation mode to output a first voltage-level shifted output signal; a second voltage-level shifter that shifts a high level of the first voltage-level shifted output signal to a further high level according to the operation mode to output a second voltage-level shifted output signal; and a word line driver that is controlled by the second voltage-level shifted output signal to drive the selected word line, wherein the second voltage-level shifter includes: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which the first voltage-level shifted output signal is supplied, the first voltage-level shifted output signal having a high and a low level according to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first voltage-level shifted output signal: a first NMOS transistor having a source connected to the second power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal as the second voltage-level sifted output signal; a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output first output terminal and a gate connected to the first input terminal; a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal; a third PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the first PMOS transistor, and a gate connected to the second output terminal; and a fourth PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the second PMOS transistor, and a gate connected to the first output terminal.
Furthermore, the present invention provides a semiconductor memory including: a memory cell array having a plurality of electrically-rewritable memory cells; a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines and bit lines of the memory cell array; a first voltage-level shifter that shifts a low level of the decoded output signal for selecting at least one of the word lines to a further low level according to an operation mode to output a first voltage-level shifted output signal; a second voltage-level shifter that shifts a high level of the first voltage-level shifted output signal to a further high level according to the operation mode to output a second voltage-level shifted output signal; and a word line driver that is controlled by the second voltage-level shifted output signal to drive the selected word line, wherein the first voltage-level shifter includes: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential; a first input terminal to which the decoded output signal is supplied, the decoded output signal having a high and a low level according to the first and the second potentials; a second input signal being an inverted signal of the first voltage-level shifted output signal; a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal as the first voltage-level shifted output signal; a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal; a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal; a third NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the first NMOS transistor, and a gate connected to the second output terminal; and a fourth NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the second NMOS transistor, and a gate connected to the first output terminal.
According to the present invention, providing transistors controlled by an input signal for current restriction along the current path in a voltage-level shifter having a pair of PMOS transistors and another pair of NMOS transistors, achieves an accurate voltage-level shifting operation.
The transistors for current restriction are NMOS transistors for shifting a low-level side of an input signal to a further low level whereas they are PMOS transistors for shifting a high-level side of an input signal to a further high level.
Provision of these transistors for current restriction requires an layout area smaller than that for increasing current capacity of transistors to be switched by an input signal.
Moreover, the present invention achieves shortening of time for a voltage-level shifting control compared to voltage-level shifting after a voltage-level shifter is switched, thus producing no unnecessary delay in operation mode control for a semiconductor device housing the voltage-level shifter according to the present invention.